Biography
Kentaro Sano received Ph.D. from the Graduate School of
Information Sciences, Tohoku University, in 2000. Since
2000 until 2005, he had been a Research Associate at
Tohoku University. Since 2005 until present, he has been
an Associate Professor at Tohoku University. Since 2017,
he had been the Leader of the Processor Research Team at
AICS, Riken. He was a visiting researcher at
Department of Computing, Imperial College, London in 2006 and 2007.
He has served several international conferences, including HEART, ICFPT, ASAP, ARC, FPL, RAW, ReconFig, and NII Shonan meeting, as a steering committee, an organizing committee, or a program committee. He has also been guest editors of IEICE Transactions on Reconfigurable Systems and International Journal of Reconfigurable Computing.
His research interests include FPGA-based high-performance reconfigurable computing, high-level synthesis compiler and tools for custom computing machines, and system architectures for supercomputing and massively-Parallel processing, especially with a tightly-coupled FPGA cluster.
Department of Computing, Imperial College, London in 2006 and 2007.
He has served several international conferences, including HEART, ICFPT, ASAP, ARC, FPL, RAW, ReconFig, and NII Shonan meeting, as a steering committee, an organizing committee, or a program committee. He has also been guest editors of IEICE Transactions on Reconfigurable Systems and International Journal of Reconfigurable Computing.
His research interests include FPGA-based high-performance reconfigurable computing, high-level synthesis compiler and tools for custom computing machines, and system architectures for supercomputing and massively-Parallel processing, especially with a tightly-coupled FPGA cluster.
Presentations
