PARADISE: A ToolFlow to Model Emerging Technologies for
the Post-CMOS Era in HPC
Contributors
Event Type
Emerging Technologies
TimeThursday, November 16th10am -
6pm
Location401
DescriptionWith the decline and eventual end of historical rates
of lithographic scaling, we arrive at a crossroad where
synergistic and holistic decisions are required to
preserve Moore’s law technology scaling. Numerous
emerging technologies aim to extend digital electronics
scaling of performance, energy efficiency, and
computational power/density, ranging from devices
(transistors), memories, 3D integration capabilities,
specialized architectures, photonics, and others. The
wide range of technology options creates the need for an
integrated strategy to understand the impact of these
emerging technologies on future large- scale digital
systems for diverse application requirements and
optimization metrics. To this end, we present PARADISE,
a comprehensive modeling suite to evaluate different
kinds of emerging technologies from the transistor level
all the way up to the architecture. We will demonstrate
how to model new devices and architectures at the low
level, and then use the characterization results as
inputs to the architectural level, and this way conduct
experiments to illustrate the high-level impact of new
devices. PARADISE is based on open-source tools and
currently uses important HPC kernels to specialize
hardware.
