P49: Toward Exascale HPC Systems: Exploiting Advances in
High Bandwidth Memory (HBM2) through Scalable All-to-All
Optical Interconnect Architectures
SessionPoster Reception
Event Type
ACM Student Research Competition
Poster
Reception
TimeTuesday, November 14th5:15pm -
7pm
LocationFour Seasons Ballroom
DescriptionAs we reach the limits of miniaturization in
fabrication processes, the interpretation of Moore's law
has changed from doubling the frequency every eighteen
months to doubling the core count every three to four
years (from 2 cores in 2004 to 16 cores in 2015). To
reach exascale-level computation, the communication and
data transfers between processors and memory is expected
to increase drastically; the on-chip interconnect plays
a key role in the overall system latency and
energy-efficiency. Therefore, novel solutions providing
one order of magnitude higher bandwidth and lower energy
consumption than what is possible with current
electrical interconnects are needed. This poster
discusses an optical interconnected compute node that
makes use of embedded photonic interconnects together
with emerging high bandwidth memory technologies (such
as HBM and HBM2). Two different multi-processors
architectures with different requirements in terms of
number of lasers, high-speed SERDES, and memory
bandwidth per processors are presented.
