Flexible Batched Sparse Matrix-Vector Product on GPUs
Author/Presenters
Event Type
Workshop
Algorithms
Exascale
Resiliency
SIGHPC Workshop
TimeMonday, November 13th11:10am -
11:30am
Location607
DescriptionWe propose a variety of batched routines for
concurrently processing a large collection of
small-size, independent sparse matrix vector products
(SpMV) on graphics processing units (GPUs). These
batched SpMV kernels are designed to be flexible in
order to handle a batch of matrices which differ in
size, nonzero count, and nonzero distribution.
Furthermore, they support three most commonly used
sparse storage formats: CSR, COO and ELL. Our
experimental results on a state-of-the-art GPU reveal
performance improvements of up to 25× compared to
non-batched SpMV routines.
