Keynote: Compiler and Runtime Challenges for Memory
Centric Programming
Author/Presenter
Event Type
Workshop
Compiler Analysis and Optimization
NVRAM
Parallel Programming Languages, Libraries, Models
and Notations
Performance
SIGHPC Workshop
TimeSunday, November 12th9:10am -
10am
Location702
DescriptionIt is widely recognized that a major disruption is
under way in computer hardware as processors strive to
extend, and go beyond, the end-game of Moore's Law. This
disruption will include new forms of processor and
memory hierarchies, including near-memory computation
structures. In this talk, we summarize compiler and
runtime challenges for memory centric programming, based
on past experiences with the X10 project at IBM and the
Habanero project at Rice University and Georgia Tech. A
key insight in addressing compiler challenges is to
expand the state-of-the-art in analyzing and
transforming explicitly-parallel programs, so as to
encourage programmers to write forward-scalable
layout-independent code rather than hardwiring their
programs to specific hardware platforms and specific
data layouts. A key insight in addressing runtime
challenges is to focus on asynchrony in both computation
and data movement, while supporting both in a unified
and integrated manner. A cross-cutting opportunity
across compilers and runtimes is to broaden the class of
computation and data mappings that can be considered for
future systems. Based on these and other insights, we
will discuss recent trends in compilers and runtime
systems that point the way towards possible directions
for addressing the challenges of memory centric
programming.
Author/Presenter
